307013-003 Datasheet, PDF (581/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.2.3.3
13.2.3.4
DATABUF[7:0]—Data Buffer Bytes[7:0] Register
Offset:
MEM_BASE + A8h–AFh
Default Value: 0000000000000000h
Attribute:
Size:
R/W
64 bits
This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register.
Bit
Description
63:0
DATABUFFER[63:0] — R/W. This field is the 8 bytes of the data buffer. Bits 7:0
correspond to least significant byte (byte 0). Bits 63:56 correspond to the most
significant byte (byte 7).
The bytes in the Data Buffer must be written with data before software initiates a write
request. For a read request, the Data Buffer contains valid data when DONE_STS bit
(offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6)
is cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0)
indicates the number of bytes that are valid.
CONFIG—Configuration Register
Offset:
MEM_BASE + B0–B3h
Default Value: 00007F01h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:15
14:8
7:4
3:0
Reserved
USB_ADDRESS_CNF — R/W. This 7-bit field identifies the USB device address used
by the controller for all Token PID generation. (Default = 7Fh)
Reserved
USB_ENDPOINT_CNF — R/W. This 4-bit field identifies the endpoint used by the
controller for all Token PID generation. (Default = 01h)
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Intel ^® ICH7 Family Datasheet
581