307013-003 Datasheet, PDF (85/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel^® ICH7 Pin States
Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 5 of 5)
Signal Name
Power
Plane
During
PLTRST#¹ /
RSMRST#²
Immediately
after
PLTRST#¹ /
RSMRST#²
S1
S3_COLD3
GPIO[39:38]
Core
Input
Input
Driven
Off
SPI Interface
SPI_CS#
SPI_MOSI
SPI_CLK
Suspend
High
High
High
High
Suspend
High
High
High
High
Suspend
Low
Low
Low
Low
Intel^® Quick Resume Technology Interface (ICH7DH Only)
EL_RSVD / GPIO26
EL_STATE[1:0] /
GPIO[28:27]
Suspend
Suspend
Low
Low
Low
Defined Defined
Low
Defined Defined
S4/S5
Off
High
High
Low
Defined
Defined
NOTES:
1.
The states of Vcc3_3 signals are taken at the times During PLTRST# and Immediately after
PLTRST#.
2.
The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately
after RSMRST#.
3.
In S3_HOT, signal states are platform implementation specific, as some external components
and interfaces may be powered when the ICH7 is in the S3_HOT state.
4.
On the ICH7, PETp/n[4:1] are high until port is enabled by software. On the ICH7R and
ICH7DH, PETp/n[6:1] are high until port is enabled by software.
5.
SLP_S5# signals will be high in the S4 state.
6.
ICH7 drives these signals High after the processor Reset.
7.
CPUPWRGD represents a logical AND of the ICH7’s VRMPWRGD and PWROK signals, and
thus will be driven low by the ICH7 when either VRMPWRGD or PWROK are inactive. During
boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition
from low to High-Z.
8.
ICH7 drives these signals Low before PWROK rising and Low after the processor Reset.
9.
Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be
Running.
10. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset
11. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the
deassertion of the RSMRST# pin.
Intel ^® ICH7 Family Datasheet
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