307013-003 Datasheet, PDF (243/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.23.1.4.2
Surprise Undock
1. In the surprise undock case the user undocks before software has had the
opportunity to gracefully halt the stream to the dock codec and initiate the
hardware undock sequence.
2. A signal on the docking connector is connected to the switch that isolates the dock
codec signals from the ICH7 HD Audio link signals (DOCK_DET# in the conceptual
diagram). When the undock event begins to occur the switch will be put into isolate
mode.
3. The undock event is communicated to the ACPI BIOS via ACPI control methods that
are outside the scope of this section of the document.
4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD
Audio Bus Driver via plug-N-play IRP. The Bus Driver then posthumously cleans up
the dock codec stream.
5. The HD Audio controller hardware is oblivious to the fact that a surprise undock
occurred. The flow from this point on is identical to the normal undocking sequence
described in section 0 starting at step 3). It finishes with the hardware clearing the
DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is
now ready for a subsequent docking event.
5.23.1.5
Interaction Between Dock/Undock and Power Management States
When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for
initiating the docking sequence if the dock is already attached when PLTRST# is de-
asserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver de-
asserting CRTS# and detecting and enumerating the codecs attached to the
AZ_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware
signal indicating that a dock is attached. Therefore, a method outside the scope of this
document must be used to cause the POST BIOS to initiate the docking sequence.
When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the
DCKCTL.DA bit is not cleared. The dock state machine will be reset such that
AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST# will be asserted and the
DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted,
the dock state machine will detect that DCKCTL.DA is set to “1” and will begin
sequencing through the dock process. Note that this does not require any software
intervention.
5.23.1.6
Relationship between AZ_DOCK_RST# and AZ_RST#
AZ_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As long
as AZ_RST# is asserted, the DOCK_RST# signal will also be asserted.
When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to
their default state (0's), and the dock state machine will be reset such that
AZ_DOCK_EN# will be de-asserted, and AZ_DOCK_RST# will be asserted. After any
PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and
then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting
CRST#.
When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state
machine will be reset such that AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST#
will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the
CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to
“1” and will begin sequencing through the dock process. Note that this does not require
any software intervention.
Intel ^® ICH7 Family Datasheet
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