307013-003 Datasheet, PDF (219/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.21
Debug Software Startup with Initialized EHCI
Debug software can attempt to use the debug port if the Current Connect Status bit in
the appropriate (See Determining the Debug Port) PORTSC register is set. If the
Current Connect Status bit is not set, then debug software may choose to terminate or
it may choose to wait until a device is connected.
If a device is connected, then debug software must set the OWNER_CNT bit and then
the ENABLED_CNT bit in the Debug Port Control/Status register.
Determining Debug Peripheral Presence
After enabling the debug port functionality, debug software can determine if a debug
peripheral is attached by attempting to send data to the debug peripheral. If all
attempts result in an error (Exception bits in the Debug Port Control/Status register
indicates a Transaction Error), then the attached device is not a debug peripheral. If the
debug port peripheral is not present, then debug software may choose to terminate or
it may choose to wait until a debug peripheral is connected.
SMBus Controller (D31:F3)
The ICH7 provides an System Management Bus (SMBus) 2.0 host controller as well as
an SMBus Slave Interface. The host controller provides a mechanism for the processor
to initiate communications with SMBus peripherals (slaves). The ICH7 is also capable of
operating in a mode in which it can communicate with I²C compatible devices.
The ICH7 can perform SMBus messages with either packet error checking (PEC)
enabled or disabled. The actual PEC calculation and checking is performed in hardware
by the ICH7.
The Slave Interface allows an external master to read from or write to the ICH7. Write
cycles can be used to cause certain events or pass messages, and the read cycles can
be used to determine the state of various status bits. The ICH7’s internal host
controller cannot access the ICH7’s internal Slave Interface.
The ICH7 SMBus logic exists in Device 31:Function 3 configuration space, and consists
of a transmit data path, and host controller. The transmit data path provides the data
flow logic needed to implement the seven different SMBus command protocols and is
controlled by the host controller. The ICH7 SMBus controller logic is clocked by RTC
clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the new Host Notify command
(which is actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done via the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
The ICH7 SMBus host controller checks for parity errors as a target. If an error is
detected, the detected parity error bit in the PCI Status Register (Device 31:Function
3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device
31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit
in the PCI Status Register (bit 14) is set.
Intel ^® ICH7 Family Datasheet
219