307013-003 Datasheet, PDF (296/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.54
GCS—General Control and Status Register
Offset Address: 3410–3413h
Default Value: 00000yy0h (yy = xx0000x0b)
Attribute:R/W, R/WLO
Size: 32-bit
Bit
31:12
Description
Reserved
Boot BIOS Straps (BBS): This field determines the destination of accesses to the
BIOS memory range. The default values for these bits represent the strap values of
GNT5#/GPIO17 (bit 11) and GNT4#/GPIO48 (bit 10) (active-high logic levels) at the
rising edge of PWROK.
11:10
Bits 11:10
00b
01b
10b
11b
Description
Reserved
SPI (supports shared flash with LAN)
PCI
LPC
When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to
FFFF_FFFFh) is accepted by the primary side of the PCI-to-PCI bridge and forwarded
to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot
from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to
be set (nor any other bits) for these cycles to go to PCI. Note that BIOS decode range
bits and the other BIOS protection bits have no effect when PCI is selected.
When SPI or LPC is selected, the range that is decoded is further qualified by other
configuration bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface
Lock-Down (bit 0) is not set.
Server Error Reporting Mode (SERM) — R/W.
0 = The Intel^® ICH7 is the final target of all errors. The (G)MCH sends a messages to
the ICH7 for the purpose of generating NMI.
9
1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this
mode, if the ICH7 detects a fatal, non-fatal, or correctable error on DMI or its
downstream ports, it sends a message to the (G)MCH. If the ICH7 receives an
ERR_* message from the downstream port, it sends that message to the
(G)MCH.
8
Reserved
7
(Mobile/
Ultra
Mobile
Only)
Mobile IDE Configuration Lock Down (MICLD) — R/WLO.
0 = Disabled.
1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system
reset occurs. This prevents rogue software from changing the default state of
the PATA pins during boot after BIOS configures them. This bit is write once, and
is cleared by system reset and when returning from the S3/S4/S5 states.
7
(Desktop ^Reserved
Only)
6
(Mobile/
Ultra
Mobile
Only)
FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break
event indication.
0 = Disabled.
1 = The ICH7-M examines FERR# during a C2, C3, or C4 state as a break event.
See Chapter 5.14.5 for a functional description.
296
Intel ^® ICH7 Family Datasheet