307013-003 Datasheet, PDF (192/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-44. SATA Feature Description
Feature
Description
Native Command Queing
(NCQ)
Auto Activate for DMA
Hot Plug Support
Asynchronous Signal
Recovery
3 Gb/s Transfer Rate
ATAPI Asynchronous
Notification
Host Initiated Power
Management
Staggered Spin-Up
Command Completion
Coalescing
Port Multiplier
External SATA
Allows the device to reorder commands for more efficient
data transfers
Collapses a DMA Setup then DMA Activate sequence into a
DMA Setup only
Allows for device detection without power being applied and
ability to connect and disconnect devices without prior
notification to the system
Provides a recovery from a loss of signal or establishing
communication after hot plug
Capable of data transfers up to 3Gb/s
A mechanism for a device to send a notification to the host
that the device requires attention
Capability for the host controller to request Partial and
Slumber interface power states
Enables the host the ability to spin up hard drives
sequentially to prevent power load problems on boot
Reduces interrupt and completion overhead by allowing a
specified number of commands to complete and then
generating an interrupt to process the commands
A mechanism for one active host connection to
communicate with multiple devices
Technology that allows for an outside the box connection of
up to 2 meters (when using the cable defined in SATA-IO)
5.17.1
5.17.1.1
Note:
5.17.1.2
Theory of Operation
Standard ATA Emulation
The ICH7 contains a set of registers that shadow the contents of the legacy IDE
registers. The behavior of the Command and Control Block registers, PIO, and DMA
data transfers, resets, and interrupts are all emulated.
The ICH7 will assert INTR when the master device completes the EDD command
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed via writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
192
Intel ^® ICH7 Family Datasheet