307013-003 Datasheet, PDF (190/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.16.4
Note:
5.16.5
Warning:
5.16.6
Ultra ATA/33/66/100 Timing
The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA
Timing register and the IDE Configuration register. Different timings can be
programmed for each drive in the system. The Base Clock frequency for each drive is
selected in the IDE Configuration register. The Cycle Time (CT) and Ready to Pause
(RP) time (defined as multiples of the Base Clock) are programmed in the Synchronous
DMA Timing Register. The Cycle Time represents the minimum pulse width of the data
strobe (STROBE) signal. The Ready to Pause time represents the number of Base Clock
periods that the ICH7 waits from deassertion of DMARDY# to the assertion of STOP
when it desires to stop a burst read transaction.
The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle
Time (CT) must be set for three Base Clocks. The ICH7 thus toggles the write strobe
signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means
that the ICH7 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For
read transfers, the read strobe is driven by the ATA/100 device, and the ICH7 supports
reads at the maximum rate of 100 MB/s.
ATA Swap Bay
To support PATA swap bay, the ICH7 allows the IDE output signals to be tri-stated and
input buffers to be turned off. This should be done prior to the removal of the drive. The
output signals can also be driven low. This can be used to remove charge built up on
the signals. Configuration bits are included in the IDE I/O Configuration register, offset
54h in the IDE PCI configuration space.
In a PATA swap bay operation, an IDE device is removed and a new one inserted while
the IDE interface is powered down and the rest of the system is in a fully powered-on
state (SO). During a PATA swap bay operation, if the operating system executes cycles
to the IDE interface after it has been powered down it will cause the ICH7 to hang the
system that is waiting for IORDY to be asserted from the drive.
To correct this issue, the following BIOS procedures are required for performing an IDE
swap:
1. Program IDE SIG_MODE (Configuration register at offset 54h) to 10b (drive low
mode).
2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing reg.). This prevents the
ICH7 from waiting for IORDY assertion when the operating system accesses the
IDE device after the IDE drive powers down, and ensures that 0s are always be
returned for read cycles that occur during swap operation.
Software should not attempt to control the outputs (either tri-state or driving low),
while an IDE transfer is in progress. Unpredictable results could occur, including a
system lockup.
SMI Trapping
Device 31:Function 1: Offset C0h (see Section 15.1.26) contain control for generating
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–
1F7h and 3F6h). Accesses to one of these ranges with the appropriate bit set causes
the cycle to not be forwarded to the IDE controller, and for an SMI# to be generated. If
an access to the Bus-Master IDE registers occurs while trapping is enabled for the
device being accessed, then the register is updated, an SMI# is generated, and the
device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating
that a trap occurred.
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Intel ^® ICH7 Family Datasheet