307013-003 Datasheet, PDF (359/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.22
BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0)
Offset Address: 48h–4Bh
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32 bits
Bit
Description
31:17 Reserved
PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the
PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the
chipset is the agent driving PERR#. It remains asserted until cleared by software
16 ^{writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the}
Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and
be a source for the NMI logic.
This bit can be used by software to determine the source of a system problem.
15:7 Reserved
Number of Pending Transactions (NPT) — RO. This field indicates to debug
software how many transactions are in the pending queue. Possible values are:
000 = No pending transaction
001 = 1 pending transaction
010 = 2 pending transactions
6:4 011 = 3 pending transactions
100 = 4 pending transactions
101 = 5 pending transactions
110 - 111 = Reserved
NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than
‘00’.
3:2 Reserved
Number of Active Transactions (NAT) — RO. This field indicates to debug software
how many transactions are in the active queue. Possible values are:
00 = No active transactions
1:0 _{01 = 1 active transaction}
10 = 2 active transactions
11 = Reserved
Intel ^® ICH7 Family Datasheet
359