307013-003 Datasheet, PDF (595/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
14.2.9
RCV_SLVA—Receive Slave Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 09h
Default Value: 44h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
Description
7 Reserved
SLAVE_ADDR — R/W. This field is the slave address that the Intel^® ICH7 decodes for
6:0
read and write cycles. the default is not 0, so the SMBus Slave Interface can respond
even before the processor comes up (or if the processor is dead). This register is
cleared by RSMRST#, but not by PLTRST#.
14.2.10 SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Ah–0Bh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bits
Resume
This register contains the 16-bit data value written by the external SMBus master. The
processor can then read the value from this register. This register is reset by RSMRST#,
but not PLTRST#
.
Bit
Description
15:8
7:0
Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.21.7 for a discussion of
this field.
Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.21.7 for a discussion of
this field.
14.2.11 AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Ch
Attribute:
R/WC, RO
Default Value: 00h
Size:
8 bits
Lockable:
No
Power Well:
Resume
.
Bit
Description
7:2 Reserved
SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible
mode vs. Advanced TCO mode.
1
0 = Intel^® ICH7 is in the compatible TCO mode.
1 = ICH7 is in the advanced TCO mode.
CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the
0
DERR bit of the host status register will also be set. This bit will be set by the
controller if a software abort occurs in the middle of the CRC portion of the cycle or
an abort happens after the ICH7 has received the final data bit transmitted by an
external slave.
Intel ^® ICH7 Family Datasheet
595