307013-003 Datasheet, PDF (176/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.12 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 5-39.
Table 5-39. Intel^® ICH7 Clock Inputs
Clock
Domain
Frequency Source
Usage
SATA_CLK
(Desktop and
Mobile Only)
100 MHz Main Clock Used by SATA controller. Stopped in S3 ~ S5 based on
Differential ^{Generator SLP_S3# assertion.}
DMI_CLK
PCICLK
CLK48
100 MHz
Differential
33 MHz
48.000
MHz
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Used by DMI and PCI Express*. Stopped in S3 ~ S5
based on SLP_S3# assertion.
Desktop Only: Free-running PCI Clock to Intel^® ICH7.
Stopped in S3 ~ S5 based on SLP_S3# assertion.
Mobile Only: Free-running (not affected by STP_PCI#
PCI Clock to ICH7. This is not the system PCI clock.
This clock must keep running in S0 while the system
PCI clock may stop based on CLKRUN# protocol.
Stopped in S3 ~ S5 based on SLP_S3# assertion.
Used by USB controllers and Intel^® High Definition
Audio controller. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
CLK14
14.318
MHz
Main Clock Used by ACPI timers. Stopped in S3 ~ S5 based on
Generator SLP_S3# assertion.
ACZ_BIT_CLK
(Desktop and
Mobile)
12.288
MHz
AC ’97
Codec
AC-link. Control policy is determined by the clock
source.
NOTE: Becomes clock output when Intel High
Definition Audio is enabled.
LAN_CLK
(Desktop and
Mobile Only)
0.8 to
50 MHz
LAN
LAN Connect Interface. Control policy is determined by
Connect the clock source.
5.14.12.1 Clock Control Signals from Intel^® ICH7 to Clock
Synthesizer (Mobile/Ultra Mobile Only)
The clock generator is assumed to have a direct connection from the following ICH7
signals:
• STP_CPU#: Stops processor clocks in C3 and C4 states
• STP_PCI#: Stops system PCI clocks (not the ICH7 free-running 33 MHz clock) due
to CLKRUN# protocol
• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop
clocks in S3_HOT and on the way to S3_COLD to S5.
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Intel ^® ICH7 Family Datasheet