307013-003 Datasheet, PDF (483/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

UHCI Controllers Registers
11.2.2
This HCHalted bit can also be used outside of Software Debug mode to indicate when
the host controller has detected the Run/Stop bit and has completed the current
transaction. Outside of the Software Debug mode, setting the Run/Stop bit to 0 always
resets the SOF counter so that when the Run/Stop bit is set the host controller starts
over again from the frame list location pointed to by the Frame List Index (see FRNUM
Register description) rather than continuing where it stopped.
USBSTS—USB Status Register
I/O Offset:
Default Value:
Base + (02h–03h)
0020h
Attribute:
Size:
R/WC
16 bits
This register indicates pending interrupts and various states of the host controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Bit
15:6
5
4
3
2
1
0
Description
Reserved
HCHalted — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has stopped executing as a result of the Run/Stop bit being set
to 0, either by software or by the host controller hardware (debug mode or an
internal error). Default.
Host Controller Process Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has detected a fatal error. This indicates that the host controller
suffered a consistency check failure while processing a Transfer Descriptor. An
example of a consistency check failure would be finding an invalid PID field while
processing the packet header portion of the TD. When this error occurs, the host
controller clears the Run/Stop bit in the Command register (D29:F0/F1/F2/
F3:BASE + 00h, bit 0) to prevent further schedule execution. A hardware interrupt
is generated to the system.
Host System Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = A serious error occurred during a host system access involving the host controller
module. In a PCI system, conditions that set this bit to 1 include PCI Parity error,
PCI Master Abort, and PCI Target Abort. When this error occurs, the host controller
clears the Run/Stop bit in the Command register to prevent further execution of
the scheduled TDs. A hardware interrupt is generated to the system.
Resume Detect (RSM_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller received a “RESUME” signal from a USB device. This is only
valid if the Host controller is in a global suspend state (Command register, D29:F0/
F1/F2/F3:BASE + 00h, bit 3 = 1).
USB Error Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Completion of a USB transaction resulted in an error condition (e.g., error counter
underflow). If the TD on which the error interrupt occurred also had its IOC bit
(D29:F0/F1/F2/F3:BASE + 04h, bit 2) set, both this bit and Bit 0 are set.
USB Interrupt (USBINT) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller sets this bit when the cause of an interrupt is a completion of a
USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a
short packet is detected (actual length field in TD is less than maximum length field
in TD), and short packet detection is enabled in that TD.
Intel ^® ICH7 Family Datasheet
483