307013-003 Datasheet, PDF (245/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.25
Serial Peripheral Interface (SPI) (Desktop and
Mobile Only)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially
lower-cost alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(CS#).
Communication on the SPI bus is done with a Master – Slave protocol. The typical bus
topology consists of a single SPI Master (ICH7) with a single SPI Slave (flash device).
The Slave is connected to the ICH7 and is implemented as a tri-state bus.
Arbitration has been added that enables an optional shared flash configuration where
the ICH7 shares access to the SPI flash device with the PCI Express based Intel PRO
82573E Gigabit Ethernet Controller. This configuration allows a single larger density
flash device to replace two smaller density flash devices on the motherboard to
potentially reduce bill of material (BOM) costs.
Note:
5.25.1
5.25.2
When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by the ICH7, LPC based BIOS flash is disabled.
SPI Arbitration between Intel^® ICH7 and Intel PRO
82573E
The Shared Flash implementation consists of two SPI masters (ICH7 and Intel PRO
82573E) that arbitrate for access to a single shared SPI Device. This allows for
consolidation of Non-Volatile memory required by the Intel PRO 82573E GbE device
with the system BIOS offering the potential for BOM and board real estate savings.
The arbitration between Intel PRO 82573E and ICH7 occurs with the addition of an ARB
signal. The SPI flash device is connected to both the Intel PRO 82573E and ICH7 chips
and implemented as a shared tri-state bus; the ARB signal is connected directly from
Intel PRO 82573E to ICH7 and not to the SPI device.
The Shared Flash configuration allows each master to complete write and erase
commands to the SPI Flash, before allowing the other master to take ownership of the
bus
Flash Device Configurations
The ICH7, Intel PRO 82573E GbE LAN with Intel^® Active Management Technology, and
SPI flash may be used in multiple configurations. Table 5-61 focuses on these various
configurations involving the ICH7.
Table 5-61. SPI Implementation Options
Configuration
Intel PRO
82573E with
Intel AMT
Present
Intel PRO
82573E
Firmware with
Intel AMT
1
No
No
2
No
No
3
Yes
SPI
4
Yes
SPI
5
Yes
SPI
System
BIOS
Location
FWH
SPI
FWH
SPI
SPI
System BIOS
and Intel
AMT Shared
Flash
No
No
No
No
Yes
FWH
Present
Yes
No
Yes
No
No
Number of
SPI
Device(s)
0
1
1
2
1
Note:
The ICH7 SPI interface supports a single Chip Select pin for a single SPI device.
Intel ^® ICH7 Family Datasheet
245