307013-003 Datasheet, PDF (443/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Bit
Description
AC97_STS — R/WC. This bit will be set to 1 when the codecs are attempting to wake
the system and the PME events for the codecs are armed for wakeup. A PME is armed
by programming the appropriate PMEE bit in the Power Management Control and
Status register at bit 8 of offset 54h in each AC ’97 function.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the codecs are attempting to wake the system. The
AC97_STS bit gets set only from the following two cases:
1. The PMEE bit for the function is set, and o The AC-link bit clock has been shut
and the routed ACZ_SDIN line is high (for audio, if routing is disabled, no
wake events are allowed).
5
2. For modem, if audio routing is disabled, then the wake event is an OR of all
ACZ_SDIN lines. If routing is enabled, then the wake event for modem is the
remaining non-routed ACZ_SDIN line), or o GPI Status Change Interrupt bit
(NABMBAR + 30h, bit 0) is 1.
NOTES:
1.
This bit is not affected by a hard reset caused by a CF9h write.
2.
This bit is also used for Intel^® High Definition Audio when ICH7 is configured
to use the Intel High Definition Audio host controller rather than the AC97
host controller.
3.
For ICH7 Ultra Mobile, only Intel High Definition is supported, AC ‘97 is not
supported.
USB2_STS — R/WC. Software clears this bit by writing a 1 to it.
4
0 = USB UHCI controller 2 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event
will be generated if the corresponding USB2_EN bit is set.
USB1_STS — R/WC. Software clears this bit by writing a 1 to it.
3
0 = USB UHCI controller 1 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event
will be generated if the corresponding USB1_EN bit is set.
SWGPE_STS — R/WC.
2
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
1
(Desktop
and
Mobile
Only)
HOT_PLUG_STS — R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the
HOT_PLUG_EN bit is set in the GEP0_EN register.
1
(Ultra
Mobile
Only)
Reserved
Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0
0 = THRM# signal Not driven active as defined by the THRM_POL bit
1 = Set by hardware anytime the THRM# signal is driven active as defined by the
THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the
THRM_STS bit will also generate a power management event (SCI or SMI#).
Intel ^® ICH7 Family Datasheet
443