307013-003 Datasheet, PDF (565/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.2.2.1
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
• Core well hardware reset
• HCRESET
• D3-to-D0 reset
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
• Suspend well hardware reset
• HCRESET
USB2.0_CMD—USB 2.0 Command Register
Offset:
MEM_BASE + 20–23h
Default Value: 00080000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:24 Reserved. These bits are reserved and should be set to 0 when writing this register.
23:16
Interrupt Threshold Control — R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Value
Maximum Interrupt Interval
00h
Reserved
01h
1 micro-frame
02h
2 micro-frames
04h
4 micro-frames
08h
8 micro-frames (default, equates to 1 ms)
10h
16 micro-frames (2 ms)
20h
32 micro-frames (4 ms)
40h
64 micro-frames (8 ms)
15:8
11:8
7
Reserved. These bits are reserved and should be set to 0 when writing this register.
Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host
controller does not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0. The Intel^® ICH7 does not implement
this optional reset.
Intel ^® ICH7 Family Datasheet
565