307013-003 Datasheet, PDF (358/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Never Prefetch (NP) — R/W.
0 = Prefetch enabled
3 _{1 = The ICH7 will only fetch a single DW and will not enable prefetching, regardless of}
the command being an Memory read (MR), Memory read line (MRL), or Memory
read multiple (MRM).
Memory Read Multiple Prefetch Disable (MRMPD) — R/W.
0 = MRM commands will fetch multiple cache lines as defined by the prefetch
2
algorithm.
1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte
aligned cache line.
Memory Read Line Prefetch Disable (MRLPD) — R/W.
1 ^{0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.}
1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned
cache line.
Memory Read Prefetch Disable (MRPD) — R/W.
0 _{0 = MR commands will fetch up to a 64-byte aligned cache line.}
1 = Memory read (MR) commands will fetch only a single DW.
358
Intel ^® ICH7 Family Datasheet