307013-003 Datasheet, PDF (803/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-10. PCI Interface Timing
Sym
Parameter
Min Max Units Notes Figure
t40 AD[31:0] Valid Delay
2
11 ns
1
23-2
t41 AD[31:0] Setup Time to PCICLK Rising
7
— ns
23-3
t42 AD[31:0] Hold Time from PCICLK Rising
0
—
ns
23-3
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
t43 PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from 2
11 ns
PCICLK Rising
1
23-2
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
t44 PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output
Enable Delay from PCICLK Rising
2
—
ns
23-6
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
t45 PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float
Delay from PCICLK Rising
2
28 ns
23-4
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
t46 SERR#, PERR#, DEVSEL#, Setup Time to PCICLK
7
—
ns
Rising
23-3
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
t47 SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time
0
—
ns
from PCLKIN Rising
23-3
t48 PCIRST# Low Pulse Width
1
— ms
23-5
GNT[5:0]# Valid Delay from PCICLK Rising
t49
NOTE: GNT[2:0]# not on Ultra Mobile.
2
12 ns
REQ[5:0]# Setup Time to PCICLK Rising
t50
NOTE: REQ[2:0]# not on Ultra Mobile.
12 —
ns
NOTES:
1. Refer to note 3 of table 4-4 in Section 4.2.2.2 and note 2 of table 4-6 in Section 4.2.3.2 of the PCI Local Bus
Specification, Revision 2.3 for measurement details.
Intel ^® ICH7 Family Datasheet
803