307013-003 Datasheet, PDF (715/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.20 TCSEL—Traffic Class Select Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 44h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register assigned the value to be placed in the TC field. CORB and RIRB data will
always be assigned TC0.
Bit
Description
7:3 Reserved.
Intel^® HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W. This
register assigns the value to be placed in the Traffic Class field for input data, output
data, and buffer descriptor transactions.
000 = TC0
001 = TC1
010 = TC2
2:0 ^{011 = TC3}
100 = TC4
101 = TC5
110 = TC6
111 = TC7
NOTE: These bits are not reset on D3_HOT to D0 transition; however, they are reset by
PLTRST#.
19.1.21 DCKCTL—Docking Control Register (Mobile Only)
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 4Ch
Default Value: 00h
Attribute:
Size:
R/W, RO
8 bits
Bit
Description
7:1 Reserved.
Dock Attach (DA) — R/W / RO:
0 = Software writes a 0 to this bit to initiate the undocking sequence on the
AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the undocking sequence is
complete, hardware will set the Dock Mated (GSTS.DM) status bit to 0.
1 = Software writes a 1 to this bit to initiate the docking sequence on the
AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the docking sequence is
0
complete, hardware will set the Dock Mated (GSTS.DM) status bit to 1.
NOTE: Software must check the state of the Dock Mated (GSTS.DM) bit prior to writing
to the Dock Attach bit. Software shall only change the DA bit from 0 to 1 when
DM=0. Likewise, software shall only change the DA bit from 1 to 0 when DM=1.
If these rules are not followed, the results are undefined.
NOTE: This bit is Read Only when the DCKSTS.DS bit = 0.
Intel ^® ICH7 Family Datasheet
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