307013-003 Datasheet, PDF (57/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
2.6
PCI Interface
Table 2-6.
PCI Interface Signals (Sheet 1 of 3)
Name
AD[31:0]
Type
Description
PCI Address/Data: AD[31:0] is a multiplexed address and data bus.
During the first clock of a transaction, AD[31:0] contain a physical
I/O address (32 bits). During subsequent clocks, AD[31:0] contain data. The
Intel^® ICH7 will drive all 0s on AD[31:0] during the address phase of all
PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address phase
of a transaction, C/BE[3:0]# define the bus command. During the data
phase, C/BE[3:0]# define the Byte Enables.
C/BE[3:0]#
DEVSEL#
FRAME#
IRDY#
C/BE[3:0]# Command Type
0000b
Interrupt Acknowledge
0001b
Special Cycle
0010b
I/O Read
0011b
I/O Write
I/O
0110b
Memory Read
0111b
Memory Write
1010b
Configuration Read
1011b
Configuration Write
1100b
Memory Read Multiple
1110b
Memory Read Line
1111b
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH7 does not
decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
Device Select: The ICH7 asserts DEVSEL# to claim a PCI transaction.
As an output, the ICH7 asserts DEVSEL# when a PCI master peripheral
attempts an access to an internal ICH7 address or an address destined
I/O DMI (main memory or graphics). As an input, DEVSEL# indicates the
response to an ICH7-initiated transaction on the PCI bus. DEVSEL# is
tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-
stated by the ICH7 until driven by a target device.
Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator asserts
FRAME#, data transfers continue. When the initiator negates FRAME#,
I/O the transaction is in the final data phase. FRAME# is an input to the
ICH7 when the ICH7 is the target, and FRAME# is an output from the
ICH7 when the ICH7 is the initiator. FRAME# remains tri-stated by the
ICH7 until driven by an initiator.
Initiator Ready: IRDY# indicates the ICH7's ability, as an initiator, to
complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY#
I/O indicates the ICH7 has valid data present on AD[31:0]. During a read, it
indicates the ICH7 is prepared to latch data. IRDY# is an input to the
ICH7 when the ICH7 is the target and an output from the ICH7 when the
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until driven by
an initiator.
Intel ^® ICH7 Family Datasheet
57