307013-003 Datasheet, PDF (138/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.9.4.6
5.9.4.7
5.9.4.8
5.9.4.9
5.9.4.10
Cascade Mode
The PIC in the ICH7 has one master 8259 and one slave 8259 cascaded onto the
master through IRQ2. This configuration can handle up to 15 separate priority levels.
The master controls the slaves through a three bit internal bus. In the ICH7, when the
master drives 010b on this bus, the slave controller takes responsibility for returning
the interrupt vector. An EOI command must be issued twice: once for the master and
once for the slave.
Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge
for the entire controller. In the ICH7, this bit is disabled and a new register for edge and
level triggered mode selection, per interrupt input, is included. This is the Edge/Level
control Registers ELCR1 and ELCR2.
If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to 1.
Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and
Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest
ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of
the PIC within the ICH7, as the interrupt being serviced currently is the interrupt
entered with the interrupt acknowledge. When the PIC is operated in modes that
preserve the fully nested structure, software can determine which ISR bit to clear by
issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if
the PIC is in the special mask mode. An EOI command must be issued for both the
master and slave controller.
Automatic End of Interrupt Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller and not
the slave controller.
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Intel ^® ICH7 Family Datasheet