307013-003 Datasheet, PDF (454/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.17 DEVACT_STS — Device Activity Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +44h
0000h
No
Core
Attribute:
Size:
Usage:
R/WC
16-bit
Legacy Only
Each bit indicates if an access has occurred to the corresponding device’s trap range, or
for bits 6:9 if the corresponding PCI interrupt is active. This register is used in
conjunction with the Periodic SMI# timer to detect any system activity for legacy power
management. The periodic SMI# timer indicates if it is the right time to read the
DEVACT_STS register (PMBASE + 44h).
Note:
Software clears bits that are set in this register by writing a 1 to the bit position.
Bit
Description
15:13
12
11:10
9
8
7
6
5:1
0
Reserved
KBC_ACT_STS — R/WC. KBC (60/64h).
0 = Indicates that there has been no access to this device’s I/O range.
1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit
location.
Reserved
PIRQDH_ACT_STS — R/WC. PIRQ[D or H].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQCG_ACT_STS — R/WC. PIRQ[C or G].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQBF_ACT_STS — R/WC. PIRQ[B or F].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQAE_ACT_STS — R/WC. PIRQ[A or E].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
Reserved
IDE_ACT_STS — R/WC. IDE Primary Drive 0 and Drive 1.
0 = Indicates that there has been no access to this device’s I/O range.
1 = This device’s I/O range has been accessed. The enable bit is in the ATC register
(D31:F1:Offset C0h). Clear this bit by writing a 1 to the bit location.
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Intel ^® ICH7 Family Datasheet