307013-003 Datasheet, PDF (211/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.20.7.4
5.20.7.5
5.20.8
5.20.8.1
ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
— The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
— When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic
processor low-power states to be entered.
— The PLL in the EHC is disabled when entering the S3_HOT state (48 MHz clock
stops), or the S3_COLD/S4/S5 states (core power turns off).
— All core well logic is reset in the S3/S4/S5 states.
Mobile/Ultra Mobile Only Considerations
The ICH7 USB 2.0 implementation does not behave differently in the mobile
configurations versus the desktop configurations. However, some features may be
especially useful for the mobile configurations.
• If a system (e.g., mobile) does not implement all eight USB 2.0 ports, the ICH7
provides mechanisms for changing the structural parameters of the EHC and hiding
unused UHCI controllers. See the Intel^® ICH7 BIOS Specification for information on
how BIOS should configure the ICH7.
• Mobile/ultra mobile systems may want to minimize the conditions that will wake the
system. The ICH7 implements the “Wake Enable” bits in the Port Status and
Control registers, as specified in the EHCI spec, for this purpose.
• Mobile/Ultra mobile systems may want to cut suspend well power to some or all
USB ports when in a low-power state. The ICH7 implements the optional Port Wake
Capability Register in the EHC Configuration Space for this platform-specific
information to be communicated to software.
Interaction with UHCI Host Controllers
The Enhanced Host controller shares the eight USB ports with four UHCI Host
controllers in the ICH7. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1
shares ports 2 and 3; the UHC at D29:F2 shares ports 4 and 5; and the UHC at D29:F3
shares ports 6 and 7 with the EHC. There is very little interaction between the
Enhanced and the UHCI controllers other than the muxing control which is provided as
part of the EHC.Figure 5-11 shows the USB Port Connections at a conceptual level.
Port-Routing Logic
Integrated into the EHC functionality is port-routing logic, which performs the muxing
between the UHCI and EHCI host controllers. The ICH7 conceptually implements this
logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of
USB 2.0’s high-speed signaling protocol or if the EHCI software drivers are not present
as indicated by the Configured Flag, then the UHCI controller owns the port. Owning
the port means that the differential output is driven by the owner and the input stream
is only visible to the owner. The host controller that is not the owner of the port
internally sees a disconnected port.
Intel ^® ICH7 Family Datasheet
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