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307013-003 Datasheet, PDF (648/848 Pages) Intel Corporation – Intel I/O Controller Hub 7 | |||
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AC â97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
17.1.1
17.1.2
17.1.3
VIDâVendor Identification Register (ModemâD30:F3)
Address Offset: 00hâ01h
Default Value: 8086
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0
Description
Vendor ID â RO. This is a 16-bit value assigned to Intel.
DIDâDevice Identification Register (ModemâD30:F3)
Address Offset: 02hâ03h
Default Value: See bit description
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0
Description
Device ID â RO. This is a 16-bit value assigned to the Intel® ICH7 AC â97 Modem
controller. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update
for the value of the Device ID Register.
PCICMDâPCI Command Register (ModemâD30:F3)
Address Offset: 04hâ05h
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification for
complete details on each bit.
Bit
Description
15:11
10
9
8
7
6
5
4
3
2
1
0
Reserved. Read 0.
Interrupt Disable (ID)â R/W.
0 = The INTx# signals may be asserted and MSIs may be generated.
1 = The AC â97 controllerâs INTx# signal will be de-asserted and it may not generate
MSIs.
Fast Back to Back Enable (FBE) â RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) â RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) â RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) â RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) â RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) â RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) â RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) â R/W. This bit controls standard PCI bus mastering
capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) â RO. Hardwired to 0, AC â97 does not respond to
memory accesses.
I/O Space Enable (IOSE) â R/W. This bit controls access to the I/O space registers.
0 = Disable access. (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
648
Intel ® ICH7 Family Datasheet
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