307013-003 Datasheet, PDF (471/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

UHCI Controllers Registers
11.1.4
Note:
PCISTS—PCI Status Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
06h–07h
0280h
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
11.1.5
Bit
Description
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when a data parity error data parity error is detected on writes to the UHCI
register space or on read completions returned to the host controller.
Reserved as 0b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = No master abort generated by USB.
1 = USB, as a master, generated a master abort.
Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
0 = Intel^® ICH7 did Not terminate transaction for USB function with a target abort.
1 = USB function is targeted with a transaction that the ICH7 terminates with a target
abort.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for
DEVSEL# assertion. These read only bits indicate the ICH7's DEVSEL# timing when
performing a positive decode. ICH7 generates DEVSEL# with medium timing for USB.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable — RO. Hardwired to 0.
Capabilities List — RO. Hardwired to 0.
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
Reserved
RID—Revision Identification Register
(USB—D29:F0/F1/F2/F3)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
Intel ^® ICH7 Family Datasheet
471