307013-003 Datasheet, PDF (612/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

IDE Controller Registers (D31:F1)
Bit
Description
Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these
bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP
(RP) time is also determined by the setting of these bits.
5:4
(Desktop
and
Mobile
Only)
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6
clocks
01 = CT 3 clocks, RP 5
clocks
10 = CT 2 clocks, RP 4
clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8
clocks
10 = CT 2 clocks, RP 8
clocks
11 = Reserved
FAST_PCB1 = 1
(133 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 16
clocks
10 = Reserved
11 = Reserved
5:4
(Ultra
and
Mobile
Only)
3:2
Reserved
Reserved
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these
bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP
(RP) time is also determined by the setting of these bits.
PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk)
FAST_PCB1 = 1
(133 MHz clk)
1:0
00 = CT 4 clocks, RP 6
clocks
00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5
clocks
01 = CT 3 clocks, RP 8
clocks
01 = CT 3 clocks, RP 16
clocks
10 = CT 2 clocks, RP 4
clocks
10 = CT 2 clocks, RP 8
clocks
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
15.1.25 IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)
Address Offset: 54h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
31:24
23:20
19:18
Description
Reserved
Miscellaneous Scratchpad (MS) — R/W. Previously defined as a scratchpad bit to
indicate to a driver that ATA-100 is supported. This is not used by software as all
they needed to know was located in bits 7:4. See the definition of those bits.
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the Intel^® ICH7.
612
Intel ^® ICH7 Family Datasheet