307013-003 Datasheet, PDF (535/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.3.2.7
PxCMD—Port [3:0] Command Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 118h
Attribute:
R/W, RO, R/WO
Port 1: ABAR + 198h (ICH7R and ICH7DH Only)
Port 2: ABAR + 218h
Port 3: ABAR + 298h (ICH7R and ICH7DH Only)
0000w00wh
Size:
32 bits
where w = 00?0b (for?, see bit description)
Bit
Description
Interface Communication Control (ICC) — R/W. This is a four bit field which can be
used to control reset and power states of the interface. Writes to this field will cause
actions on the interface, either as primitives or an OOB sequence, and the resulting
status of the interface will be reported in the PxSSTS register (Address offset Port
0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h).
31:28
Value
Fh–7h
6h
5h–3h
2h
1h
0h
Definition
Reserved
Slumber: This will cause the Intel^® ICH7 to request a transition of the
interface to the slumber state. The SATA device may reject the request
and the interface will remain in its current state
Reserved
Partial: This will cause the ICH7 to request a transition of the interface
to the partial state. The SATA device may reject the request and the
interface will remain in its current state.
Active: This will cause the ICH7 to request a transition of the interface
into the active
No-Op / Idle: When software reads this value, it indicates the ICH7 is
not in the process of changing the interface state or sending a device
reset, and a new link command may be issued.
When system software writes a non-reserved value other than No-Op (0h), the ICH7 will
perform the action and update this field back to Idle (0h).
If software writes to this field to change the state to a state the link is already in (e.g.
interface is in the active state and a request is made to go to the active state), the ICH7
will take no action and return this field to Idle.
NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or
06h.
Aggressive Slumber / Partial (ASP) — R/W. When set, and the ALPE bit (bit 26) is
set, the ICH7 will aggressively enter the slumber state when it clears the PxCI register
27 and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the ICH7 will
aggressively enter the partial state when it clears the PxCI register and the PxSACT
register is cleared.
Aggressive Link Power Management Enable (ALPE) — R/W. When set, the ICH7
26 will aggressively enter a lower link power state (partial or slumber) based upon the
setting of the ASP bit (bit 27).
Drive LED on ATAPI Enable (DLAE) — R/W. When set, the ICH7 will drive the LED
25
pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When
cleared, the ICH7 will only drive the LED pin active for ATA commands. See
Section 5.17.5 for details on the activity LED.
HDevice is ATAPI (ATAPI) — R/W. When set, the connected device is an ATAPI
24 device. This bit is used by the ICH7 to control whether or not to generate the desktop
LED when commands are active. See Section 5.17.5 for details on the activity LED.
23:20 Reserved
Intel ^® ICH7 Family Datasheet
535