307013-003 Datasheet, PDF (7/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

5.15
5.16
5.17
5.14.8.4 Active Cooling ........................................................................ 167
5.14.9 Event Input Signals and Their Usage ....................................................... 167
5.14.9.1 PWRBTN# (Power Button) ........................................................ 167
5.14.9.2 RI# (Ring Indicator)................................................................ 168
5.14.9.3 PME# (PCI Power Management Event) ....................................... 169
5.14.9.4 SYS_RESET# Signal ................................................................ 169
5.14.9.5 THRMTRIP# Signal.................................................................. 169
5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) ....................................... 170
5.14.10ALT Access Mode .................................................................................. 170
5.14.10.1Write Only Registers with Read Paths in ALT Access Mode............. 171
5.14.10.2PIC Reserved Bits ................................................................... 173
5.14.10.3Read Only Registers with Write Paths in ALT Access Mode............. 173
5.14.11System Power Supplies, Planes, and Signals ............................................ 173
5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173
5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 174
5.14.11.3PWROK Signal ........................................................................ 174
5.14.11.4CPUPWRGD Signal .................................................................. 175
5.14.11.5VRMPWRGD Signal.................................................................. 175
5.14.11.6BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175
5.14.11.7Controlling Leakage and Power Consumption during Low-Power
States ................................................................................... 175
5.14.12Clock Generators.................................................................................. 176
5.14.12.1Clock Control Signals from Intel^® ICH7 to Clock
Synthesizer (Mobile/Ultra Mobile Only)....................................... 176
5.14.13Legacy Power Management Theory of Operation ....................................... 177
5.14.13.1APM Power Management (Desktop Only) .................................... 177
5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only) ........... 177
System Management (D31:F0).......................................................................... 178
5.15.1 Theory of Operation.............................................................................. 178
5.15.1.1 Detecting a System Lockup ...................................................... 178
5.15.1.2 Handling an Intruder ............................................................... 178
5.15.1.3 Detecting Improper Firmware Hub Programming ......................... 179
5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179
IDE Controller (D31:F1) ................................................................................... 183
5.16.1 PIO Transfers ....................................................................................... 183
5.16.1.1 PIO IDE Timing Modes ............................................................. 184
5.16.1.2 IORDY Masking....................................................................... 184
5.16.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 184
5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185
5.16.2 Bus Master Function ............................................................................. 185
5.16.2.1 Physical Region Descriptor Format............................................. 185
5.16.2.2 Bus Master IDE Timings ........................................................... 186
5.16.2.3 Interrupts .............................................................................. 186
5.16.2.4 Bus Master IDE Operation ........................................................ 187
5.16.2.5 Error Conditions...................................................................... 188
5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188
5.16.3.1 Operation .............................................................................. 189
5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190
5.16.5 ATA Swap Bay...................................................................................... 190
5.16.6 SMI Trapping ....................................................................................... 190
SATA Host Controller (D31:F2) (Desktop and Mobile Only) .................................... 191
5.17.1 Theory of Operation.............................................................................. 192
5.17.1.1 Standard ATA Emulation .......................................................... 192
5.17.1.2 48-Bit LBA Operation............................................................... 192
5.17.2 SATA Swap Bay Support ........................................................................ 193
5.17.3 Intel^® Matrix Storage Technology Configuration (Intel^® ICH7R, ICH7DH,
and ICH7-M DH Only) ........................................................................... 193
Intel ^® ICH7 Family Datasheet
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