307013-003 Datasheet, PDF (518/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bits
Description
9
(Mobile
Only)
8
7:2
1:0
Reserved.
Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detected on this bit
field, the ICH7 initiates a BIST FIS to the device on Port 0, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will
only be initiated if a device on Port 0 is present and ready (not partial/slumber state).
After a BIST FIS is successfully completed, software must disable and re-enable the
port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to
return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P0BFI bit
to initiate another BIST FIS. This can be retried until the BIST FIS eventually
completes successfully
BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the BIST
FIS Pattern Definition in any BIST FIS transmitted by the ICH7. This field is not port
specific; its contents will be used for any BIST FIS initiated on port 0, port 1, port 2 or
port 3. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
Bit 6: A – Align Bypass mode
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
Reserved
12.1.44 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset: E4h–E7h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bits
Description
31:0
BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form
the contents of the second DWord of any BIST FIS initiated by the Intel^® ICH7. This
register is not port specific; its contents will be used for BIST FIS initiated on any port.
Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of
the BIST FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be
transmitted as the BIST FIS 2nd DW regardless of whether or not the “T” bit is indicated
in the BFCS register (D31:F2:E0h).
518
Intel ^® ICH7 Family Datasheet