307013-003 Datasheet, PDF (332/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.4
ASF_CNTL_EN—ASF Control Enable Register
(ASF Controller—B1:D8:F0)
Offset Address: E3h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is used to enable global processing as well as polling. GLOBAL ENABLE
controls all of the SMBus processing and packet creation.
Bit
Description
Global Enable (CENA_ALL) — R/W.
7 0 = Disable
1 = All control and polling enabled
Receive Enable (CENA_RX) — R/W.
6 _{0 = Disable}
1 = TCO Receives enabled.
Transmit Enable (CENA_TX) — R/W.
5 _{0 = Disable}
1 = SOS and RMCP Transmits enabled
ASF Polling Enable (CENA_APOL) — R/W.
4 _{0 = Disable}
1 = Enable ASF Sensor Polling.
Legacy Polling Enable (CENA_LPOL) — R/W.
3 0 = Disable
1 = Enable Legacy Sensor Polling.
Number of Legacy Poll Devices (CENA_NLPOL) — R/W. This 3-bit value indicates
how many of the eight possible polling descriptors are active.
000 = First polling descriptor is active.
2:0 _{001 = First two polling descriptors are active.}
...
111 = Enables all eight descriptors.
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Intel ^® ICH7 Family Datasheet