307013-003 Datasheet, PDF (246/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.25.3
5.25.3.1
Note:
5.25.3.2
SPI Device Compatibility Requirements
A variety of SPI flash devices exist in the market. In order for a SPI device to be
compatible with the ICH7 it must meet the minimum requirements detailed in the
following sections.
Intel^® ICH7 SPI Based BIOS Only Configuration Requirements
(Non-Shared Flash Configuration)
A SPI flash device must meet the following minimum requirements to be compatible
with the ICH7 in a non-shared flash configuration:
• Erase size capability of at least one of the following: 64 KB, 32 KB, 4 KB, 2 KB, 512
bytes, or 256 bytes.
• Required command set and associated opcodes (Refer to Section 5.25.4.1).
• Device identification command (Refer to Section 5.25.4.2).
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.25.4.3)
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh simply aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported, the device must complete
the cycle gracefully without any impact on the flash content.
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
inside the designated area (page, sector, block, chip, or etc.).
• Minimum density of 4 Mb (Platform dependent based on size of BIOS).
The ICH7 only supports Mode 0 on SPI flash devices
Intel^® ICH7 with Intel^® PRO 82573E with Intel AMT Firmware
Configuration Requirements (Shared Flash Configuration)
A SPI flash device must meet the following minimum requirements to be compatible
with the ICH7 and the Intel PRO 82573E GbE with Intel AMT device in a shared flash
configuration:
The following are requirements that are in common with the BIOS only configuration
listed in Section 5.25.3.1:
• Required command set and associated opcodes (Refer to Section 5.25.4.1)
• Device identification command (Refer to Section 5.25.4.2)
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.25.4.3)
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh simply aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported, the device must complete
the cycle gracefully without any impact on the flash content.
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
inside the designated area (page, sector, block, chip, or etc.).
246
Intel ^® ICH7 Family Datasheet