307013-003 Datasheet, PDF (28/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

19.2.42SDFIFOS—Stream Descriptor FIFO Size Register
(Intel^® High Definition Audio Controller—D27:F0) ..................................... 755
19.2.43SDFMT—Stream Descriptor Format Register
(Intel^® High Definition Audio Controller—D27:F0) ..................................... 756
19.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base
Address Register (Intel^® High Definition Audio Controller—D27:F0) ............. 757
19.2.45SDBDPU—Stream Descriptor Buffer Descriptor List PointerUpper Base
Address Register (Intel^® High Definition Audio Controller—D27:F0) ............. 757
20 High Precision Event Timer Registers..................................................................... 759
20.1 Memory Mapped Registers ................................................................................ 759
20.1.1 GCAP_ID—General Capabilities and Identification Register.......................... 760
20.1.2 GEN_CONF—General Configuration Register ............................................. 761
20.1.3 GINTR_STA—General Interrupt Status Register ......................................... 761
20.1.4 MAIN_CNT—Main Counter Value Register ................................................. 762
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register...................... 762
20.1.6 TIMn_COMP—Timer n Comparator Value Register ...................................... 764
21 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) ................................. 765
21.1 Serial Peripheral Interface Memory Mapped Configuration Registers ........................ 765
21.1.1 SPIS—SPI Status Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 767
21.1.2 SPIC—SPI Control Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 768
21.1.3 SPIA—SPI Address Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 769
21.1.4 SPID[N] —SPI Data N Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 769
21.1.5 BBAR—BIOS Base Address Register
(SPI Memory Mapped Configuration Registers).......................................... 770
21.1.6 PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 770
21.1.7 OPTYPE—Opcode Type Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 771
21.1.8 OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 772
21.1.9 PBR[N]—Protected BIOS Range [N]
(SPI Memory Mapped Configuration Registers).......................................... 772
22 Ballout Definition ................................................................................................... 773
22.1 Desktop, Mobile, and Digital Home Component Ballout.......................................... 773
22.2 Ultra Mobile Component Ballout ......................................................................... 782
23 Electrical Characteristics........................................................................................ 789
23.1 Thermal Specifications...................................................................................... 789
23.2 Absolute Maximum Ratings ............................................................................... 789
23.3 DC Characteristics ........................................................................................... 790
23.4 AC Characteristics............................................................................................ 801
23.5 Timing Diagrams ............................................................................................. 817
24 Package Information ............................................................................................. 835
24.1 Desktop and Mobile Package Information ............................................................ 835
24.2 Ultra Mobile Package Information ....................................................................... 837
25 Testability (Desktop and Mobile Only).................................................................... 839
25.1 XOR Chain Tables............................................................................................. 841
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Intel ^® ICH7 Family Datasheet