307013-003 Datasheet, PDF (89/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel^® ICH7 Pin States
Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 4 of 4)
Signal Name
Power
Plane
During
PLTRST#¹ /
RSMRST#²
Immediately
after
PLTRST#¹ /
RSMRST#²
C3/C4
S1
S3_COLD3
S4/
S5
ACZ_BIT_CLK
Core
High-Z with
Internal Pull-
down
Low¹¹
Running
Low
Off
Off
AZ_DOCK_RST# /
GPIO34
Core
Low
Low¹¹
Defined Defined
Off
Off
AZ_DOCK_EN# /
GPIO33
Core
High
High
Defined Defined
Off
Off
Unmultiplexed GPIO Signals
GPIO[7:6]
GPIO[15:12,10:8]
GPIO18
GPIO19
GPIO24
Core
Suspend
Core
Core
Suspend
GPIO25
Suspend
GPIO[28:26]
GPIO[39:37]
Suspend
Core
Input
Input
High
Input
No Change
High
Low
Input
Input
Input
See Note 12
Input
No Change
High¹³
Low
Input
Driven
Driven
Driven
Driven
Defined
Defined
Defined
Driven
Driven
Driven
Driven
Driven
Defined
Defined
Defined
Driven
Off
Driven
Off
Off
Defined
Defined
Defined
Off
Off
Driven
Off
Off
Define
d
Define
d
Define
d
Off
SPI Interface (Mobile Only)
SPI_CS#
SPI_MOSI
SPI_ARB
SPI_CLK
Suspend
Suspend
Suspend
Suspend
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
NOTES:
1.
The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after
PLTRST#.
2.
The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately
after RSMRST#.
3.
In S3_HOT, signal states are platform implementation specific, as some external components
and interfaces may be powered when the Intel^® ICH7 is in the S3_HOT state.
4.
PETp/n[6:1] high until port is enabled by software.
5.
LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3–S5 states
depending upon whether or not the LAN power planes are active.
6.
SLP_S5# signals will be high in the S4 state.
7.
The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled
or low if it is disabled.
8.
ICH7 drives these signals High after the processor Reset.
9.
CPUPWRGD is an output that represents a logical AND of the Intel^® ICH7’s VRMPWRGD
and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or
PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD
will be expected to transition from low to High.
10. IICH7 drives these signals Low before PWROK rising and Low after the processor Reset.
Intel ^® ICH7 Family Datasheet
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