307013-003 Datasheet, PDF (816/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-23. Power Management Timings (Sheet 3 of 3)
Sym
Parameter
Min Max Units Notes Fig
t298 SLP_S4# inactive to SLP_S3# inactive
t299
S4 Wake Event to SLP_S4# inactive (S4
Wake)
t300
S3 Wake Event to SLP_S3# inactive (S3
Wake)
CPUSLP# inactive to STPCLK# inactive
t301
(Desktop Only)
t302
SLP_S3# inactive to ICH7 check for PWROK
active
t303 SLP_S3# active to Vcc supplies inactive
1
2 RTCCLK
See Note Below
small
0
as
possi
RTCCLK
ble
8
PCICLK
4
5
msec
5
us
4
3
4
15, 17
23-23
23-24
23-25
23-26
23-23
23-24
23-25
23-26
23-23
23-24
23-25
23-26
23-22
23-23
23-24
23-25
23-26
Other Timings
t310
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
3 PCI CLK
t311 RSMRST# rising edge transition from 20% to 80%
t312 RSMRST# falling edge transition
50
us
18
NOTES:
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
2. If the AFTERG3_EN bit (GEN_PMCON_3 Configuration Register Bit 1) is set to a 1, SLP_S5# will not be de-
asserted until a wake event is detected. If the AFTERG3_EN bit is set to 0, SLP_S5# will deassert within the
specification listed in the table.
3. The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the
“SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).
4. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 28.992 µs to 32.044 µs.
5. Note that this does not apply for synchronous SMIs.
6. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
7. This is a clock generator specification.
8. This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert time for DPRSLPVR
has been met, then this is permitted to be 0.
9. This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert time for STP_CPU#
has been met, then this is permitted to be 0.
10.This value should be at most a few clocks greater than the minimum.
11.This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 µs).
12.The ICH7 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing for
this cycle getting to the ICH7 is dependant on the processor and the memory controller.
13.The ICH7 has no maximum timing requirement for this transition. It is up to the system designer to determine
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
14.t290, t293, and t294 apply during S0 to G3 transitions only. In addition, the timings are not applied to V5REF.
V5REF timings are bonded by power sequencing.
15.A Vcc supply is inactive when the voltage is below the min value specified in Table 23-8.
16.If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together
similar to timing t287 (PCIRST# active to SLP_S3# active).
17.t303 applies during S0 to S3-S5 transitions.
18.RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.1 V.
816
Intel ^® ICH7 Family Datasheet