307013-003 Datasheet, PDF (498/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.15.2 AHCI Capable (Intel^® ICH7R, ICH7DH, and Mobile Only)
Address Offset: 24h–27h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
This register allocates space for the memory registers defined in Section 12.3. For non-
ACHI capable ICH7 components (ICH7), this register is reserved and read only, unless
the SCRAE bit (offset 94h:bit 9) is set, in which case the register follows the definition
given in Section 12.1.15.2.
Bit
Description
31:10 Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB)
9:4 Reserved
3 Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable
2:1
Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address
space.
0
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register
memory space.
NOTES:
1.
.When the MAP.MV register is programmed for combined mode (00b), this register is RO.
Software is responsible for clearing this bit before entering combined mode.
2.
The ABAR register must be set to a value of 0001_0000h or greater.
12.1.16 SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset: 2Ch–2Dh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
Bit
Description
15:0
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware
action taken on this value.
12.1.17 SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh–2Fh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
Bit
Description
15:0
Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
498
Intel ^® ICH7 Family Datasheet