307013-003 Datasheet, PDF (341/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.20
PHIST_CLR—Poll History Clear Register
(ASF Controller—B1:D8:F0)
Offset Address: F7h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
This register is used to clear the history of the Legacy Poll operations. ASF maintains
history of the last poll data for each Legacy Poll operation to compare against the
current poll to detect changes. By setting the appropriate bit, the history for that
Legacy Poll is cleared to 0s.
Bit
Description
Clear Polling Descriptor 8 History (PHC_POLL8) — R/WC. Writing a 1b to this bit
7 position will clear the Poll History associated with Polling Descriptor #8. Writing a 0b
has no effect.
Clear Polling Descriptor 7 History (PHC_POLL7) — R/WC. Writing a 1b to this bit
6 position will clear the Poll History associated with Polling Descriptor #7. Writing a 0b
has no effect.
Clear Polling Descriptor 6 History (PHC_POLL6) — R/WC. Writing a 1b to this bit
5 position will clear the Poll History associated with Polling Descriptor #6. Writing a 0b
has no effect.
Clear Polling Descriptor 5 History (PHC_POLL5) — R/WC. Writing a 1b to this bit
4 position will clear the Poll History associated with Polling Descriptor #5. Writing a 0b
has no effect.
Clear Polling Descriptor 4 History (PHC_POLL4) — R/WC. Writing a 1b to this bit
3 position will clear the Poll History associated with Polling Descriptor #4. Writing a 0b
has no effect.
Clear Polling Descriptor 3 History (PHC_POLL3) — R/WC. Writing a 1b to this bit
2 position will clear the Poll History associated with Polling Descriptor #3. Writing a 0b
has no effect.
Clear Polling Descriptor 2 History (PHC_POLL2) — R/WC. Writing a 1b to this bit
1 position will clear the Poll History associated with Polling Descriptor #2. Writing a 0b
has no effect.
Clear Polling Descriptor 1 History (PHC_POLL1) — R/WC. Writing a 1b to this bit
0 position will clear the Poll History associated with Polling Descriptor #1. Writing a 0b
has no effect.
8.3.21
PMSK1—Polling Mask 1 Register
(ASF Controller—B1:D8:F0)
Offset Address: F8h
Default Value: XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #1 Data Mask.
Bit
Description
Polling Mask for Polling Descriptor #1 (POL1_MSK) — R/W. This field is used to
7:0 read and write the data mask for Polling Descriptor #1. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Intel ^® ICH7 Family Datasheet
341