307013-003 Datasheet, PDF (441/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Bit
Description
PME_B0_STS — R/WC. This bit will be set to 1 by the Intel^® ICH7 when any internal
device with PCI Power Management capabilities on bus 0 asserts the equivalent of the
PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an S0
state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if
SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4 state
13
(or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit
will generate a wake event, and an SCI (or SMI# if SCI_EN is not set) will be
generated. If the system is in an S5 state due to power button override, then the
PME_B0_STS bit will not cause a wake event or SCI.
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
USB3_STS — R/WC.
0 = Disable.
12
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set when USB UHCI controller #3 needs to cause a
wake. Additionally if the USB3_EN bit is set, the setting of the USB3_STS bit will
generate a wake event.
11
10
(Desktop
Only)
PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN
bit is set, and the system is in an S0 state, then the setting of the PME_STS bit
will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and
the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and
SLP_EN), then the setting of the PME_STS bit will generate a wake event, and an
SCI will be generated. If the system is in an S5 state due to power button
override or a power failure, then PME_STS will not cause a wake event or SCI.
Intel^® ICH7DH Only:
EL_SCI_STS — R/WC. In Desktop Mode, when Intel Quick Resume Technology
feature is enabled, this bit will be set by hardware when the SCI_NOW_CNT or
EL_PB_SCI_STS bit goes high. Software clears the bit by writing a 1 to the bit
position.
In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit
will be treated as Reserved.
ICH7 and ICH7R Only:
Reserved
10
(Mobile/
Ultra
Mobile
Only)
BATLOW_STS — R/WC. (Mobile/Ultra Mobile Only) Software clears this bit by
writing a 1 to it.
0 = BATLOW# Not asserted
1 = Set by hardware when the BATLOW# signal is asserted.
Intel ^® ICH7 Family Datasheet
441