307013-003 Datasheet, PDF (605/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

IDE Controller Registers (D31:F1)
15.1.10 PMLT—Primary Master Latency Timer Register
(IDE—D31:F1)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
Master Latency Timer Count (MLTC) — RO.
7:0 _{00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as}
a PCI device, so it does not need a Master Latency Timer.
15.1.11 PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)
Address Offset: 10h–13h
Default Value: 00000001h
.
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:16 Reserved
15:3 Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
15.1.12 PCNL_BAR—Primary Control Block Base Address
Register (IDE—D31:F1)
Address Offset: 14h–17h
Default Value: 00000001h
.
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:16 Reserved
15:2 Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations).
1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
Intel ^® ICH7 Family Datasheet
605