307013-003 Datasheet, PDF (511/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bits
0
Description
Port 0 Enabled (P0E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1)
12.1.35 SIR—SATA Initialization Register
Address Offset: 94h–97h
Default Value: 00000000h
.
Attribute:
Size:
R/W
32 bits
Bit
Description
31:29 Reserved
SATA Capability Registers Disable (SCRD).
When this bit is set, the SATA Capability Registers are disabled. That is, SATA
Capability Registers 0 and 1 are both changed to Read Only with the value of
30
00000000h. Also, the Next Capability bits in the PCI Power Management Capability
Information Register (D31:F2;Offset 70h bits 15:8) are changed to 00h, to indicate
that the PCI Power Management Capability structure is the last PCI capability
structure in the SATA controller. When this bit is cleared, the SATA Capability
Registers are enabled.
29
Reserved
SATA Clock Request Enabled (SCRE) — R/W.
0 = SATA Clock Request protocol is disabled. SATACLKREQ# pin when in native
28
function will always output '0' to keep the SATA clock running.
1 = SATA Clock Request protocol is enabled. SATACLKREQ# pin when in native
function will behave as the Serial ATA clock request to the system clock chip.
27:24
(Desktop
Only)
Reserved
27:24
(Mobile
Only)
SATA Initialization Field 3 (SIF3) — R/W. BIOS shall always program this
register to the value 0Ah. All other values are reserved.
23
SATA Initialization Field 2 (SIF2) — R/W. BIOS shall always program this
register to the value 1b. All other values are reserved.
22:10 Reserved
SCR Access Enable (SCRAE) — R/W. In non-AHCI mode, this bit allows access to
the SATA SCR registers (SStatus, SControl, and SError registers).
0 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset
04h:bit 1) remain as defined.
1 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset
04h:bit 1) are forced to be read/write.
9
NOTES:
1.
Using this mode only allows access to AHCI registers PxSSTS, PxSCTL,
PxSERR. All other AHCI space is reserved when this bit is set.
2.
Proper use of this bit requires:
• ABAR must be programmed to a valid BAR; MSE must be set before software can access
AHCI space.
• The Port Implemented bit (D31:F2, Offset ABAR+0Ch) for the corresponding port has to be
set to allow access to the AHCI port specific PxSSTS, PxSCTL, and PxSERR registers.
Intel ^® ICH7 Family Datasheet
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