307013-003 Datasheet, PDF (627/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.15 SID—Subsystem Identification Register (Audio—D30:F2)
Address Offset: 2Eh–2Fh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
The SID register, in combination with the Subsystem Vendor ID register (D30:F2:2Ch)
make it possible for the operating environment to distinguish one audio subsystem
from the other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3_HOT to D0 transition.
T
Bit
15:0
Subsystem ID — R/WO.
Description
16.1.16 CAP_PTR—Capabilities Pointer Register (Audio—D30:F2)
Address Offset: 34h
Default Value: 50h
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
This register indicates the offset for the capability pointer.
Bit
Description
7:0
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer
offset is offset 50h
16.1.17 INT_LN—Interrupt Line Register (Audio—D30:F2)
Address Offset: 3Ch
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.
Bit
Description
7:0
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel^® ICH7. It is used
to communicate to software the interrupt line that the interrupt pin is connected to.
Intel ^® ICH7 Family Datasheet
627