307013-003 Datasheet, PDF (390/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.2.7
DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Bh;
Ch. #4–7 = D6h
0000 00xx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four
different modes:
00 = Demand mode
7:6 _{01 = Single mode}
10 = Reserved
11 = Cascade mode
Address Increment/Decrement Select — WO. This bit controls address increment/
decrement during DMA transfers.
5
0 = Address increment. (default after part reset or Master Clear)
1 = Address decrement.
Autoinitialize Enable — WO.
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count.
4
A part reset or Master Clear disables autoinitialization.
1 = DMA restores the Base Address and Count registers to the current registers
following a terminal count (TC).
DMA Transfer Type — WO. These bits represent the direction of the DMA transfer.
When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type
is irrelevant.
3:2 ^{00 = Verify – No I/O or memory strobes generated}
01 = Write – Data transferred from the I/O devices to memory
10 = Read – Data transferred from memory to the I/O device
11 = Invalid
DMA Channel Select — WO. These bits select the DMA Channel Mode Register that
will be written by bits [7:2].
00 = Channel 0 (4)
1:0 _{01 = Channel 1 (5)}
10 = Channel 2 (6)
11 = Channel 3 (7)
390
Intel ^® ICH7 Family Datasheet