307013-003 Datasheet, PDF (71/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
2.19 AC ’97/Intel^® High Definition Audio Link
Note:
AC ‘97 is not supported on Ultra Mobile.
Table 2-19. AC ’97/Intel^® High Definition Audio Link Signals
Name^1,2
Type
Description
ACZ_RST#
O
AC ’97/Intel^® High Definition Audio Reset: This signal is the
master hardware reset to external codec(s).
ACZ_SYNC
AC ’97/Intel High Definition Audio Sync: This signal is a 48 kHz
O fixed rate sample sync to the codec(s). It is also used to encode the
stream number.
ACZ_BIT_CLK
ACZ_SDOUT
AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data
clock generated by the external codec(s). This signal has an
integrated pull-down resistor (see Note below).
Intel High Definition Audio Bit Clock Output: This signal is a
I/O _{24.000 MHz serial data clock generated by the Intel High Definition}
Audio controller (the Intel^® ICH7). This signal has an integrated pull-
down resistor so that ACZ_BIT_CLK doesn’t float when an Intel High
Definition Audio codec (or no codec) is connected but the signals are
temporarily configured as AC ’97.
AC ’97/Intel High Definition Audio Serial Data Out: This signal
is the serial TDM data output to the codec(s). This serial output is
double-pumped for a bit rate of 48 Mb/s for Intel High Definition
O
Audio.
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a
functional strap. See Section 2.24.1 for more details. There is
a weak integrated pull-down resistor on the ACZ_SDOUT pin.
ACZ_SDIN[2:0]
AZ_DOCK_EN#
(Mobile Only) /
GPIO33
AC ’97/Intel High Definition Audio Serial Data In [2:0]: These
signals are serial TDM data inputs from the three codecs. The serial
I
input is single-pumped for a bit rate of 24 Mb/s for Intel^® High
Definition Audio. These signals have integrated pull-down resistors
that are always enabled.
High Definition Audio Dock Enable: This signal controls the
external Intel HD Audio docking isolation logic. This is an active low
signal. When deasserted, the external docking switch is in isolate
mode. When asserted, the external docking switch electrically
connects the Intel HD Audio dock signals to the corresponding Intel^®
I/O _{ICH7 signals.}
This signal is shared with GPIO33. This signal defaults to GPIO33
mode after PLTRST# reset and will be in the high state after
PLTRST# reset. BIOS is responsible for configuring GPIO33 to
AZ_DOCK_EN# mode.
High Definition Audio Dock Reset: This signal is a dedicated
AZ_RST# signal for the codec(s) in the docking station. Aside from
operating independently from the normal ACZ_RST# signal, it
AZ_DOCK_RST#
otherwise works similarly to the ACZ_RST# signal.
(Mobile Only) / I/O
GPIO34
This signal is shared with GPIO34. This signal defaults to GPIO34
mode after PLTRST# reset and will be in the low state after PLTRST#
reset. BIOS is responsible for configuring GPIO34 to
AZ_DOCK_RST# mode.
NOTES:
1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details.
2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode
of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0 AC ‘97 mode is selected. When set to
1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode).
Intel ^® ICH7 Family Datasheet
71