307013-003 Datasheet, PDF (349/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.5
9.1.6
Bit
11
10:9
8
7:5
4
3
2:0
Description
Signaled Target Abort (STA) — R/WC.
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the
backbone.
Reserved.
Data Parity Error Detected (DPD) — R/WC.
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a
previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit
6).
Reserved.
Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate
interrupts.
Reserved
RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h-0Bh
Default Value: 060401h
Attribute:
Size:
RO
24 bits
Bit
Description
23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
15:8
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI
bridge.
7:0
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractive
decode
Intel ^® ICH7 Family Datasheet
349