307013-003 Datasheet, PDF (259/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Register and Memory Mapping
Table 6-3. Variable I/O Decode Ranges
Range Name
Mappable
LAN
LPC Generic 1
LPC Generic 2¹
LPC Generic 3
LPC Generic 4
I/O Trapping Ranges
Anywhere in 64 KB I/O
Space
Anywhere in 64 KB I/O
Space
Anywhere in 64 KB I/O
Space
Anywhere in 64 KB I/O
Space
Anywhere in 64 KB I/O
Space
Anywhere in 64 KB I/O
Space
Size
(Bytes)
64
Target
LAN Unit
4 to 256
LPC Peripheral
4 to 256
LPC Peripheral
4 to 256
LPC Peripheral
4 to 256
LPC Peripheral
1 to 256 Trap on Backbone
NOTE:
1.
Decode range size determined by D31:F0:ADh:bits 5:4
6.4
Memory Map
Table 6-4 shows (from the processor perspective) the memory ranges that the ICH7
decodes. Cycles that arrive from DMI that are not directed to any of the internal
memory targets that decode directly from DMI will be driven out on PCI unless the
Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The ICH7 may then
claim the cycle for the internal LAN controller.
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to DMI. Software must not attempt locks to the ICH7’s memory-
mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which
means potential deadlock conditions may occur.
Table 6-4.
Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
Memory Range
0000 0000h–000D FFFFh
0010 0000h–TOM
(Top of Memory)
000E 0000h–000E FFFFh
000F 0000h–000F FFFFh
FEC0 0000h–FEC0 0100h
FED4 0000h–FED4 0FFFh
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
Target
Dependency/Comments
Main Memory
TOM registers in Host controller
Firmware Hub
Firmware Hub
I/O APIC inside
Intel^® ICH7
TPM on LPC
Firmware Hub (or
PCI)¹
Firmware Hub (or
PCI)¹
Bit 6 in Firmware Hub Decode Enable register
is set
Bit 7 in Firmware Hub Decode Enable register
is set
Bit 8 in Firmware Hub Decode Enable register
is set
Bit 9 in Firmware Hub Decode Enable register
is set
Intel ^® ICH7 Family Datasheet
259