307013-003 Datasheet, PDF (431/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3 Power Management I/O Registers
Table 10-11 shows the registers associated with ACPI and Legacy power management
support. These registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers
are defined to support the ACPI 2.0 specification, and use the same bit names.
Note:
All reserved bits and registers will always return 0 when read, and will have no effect
when written.
Table 10-11. ACPI and Legacy I/O Register Map (Sheet 1 of 2)
PMBASE
+ Offset
Mnemonic
Register Name
ACPI Pointer
Default
Type
00h–01h
PM1_STS
PM1 Status
PM1a_EVT_BLK
0000h
R/WC
02h–03h
PM1_EN
PM1 Enable
PM1a_EVT_BLK+2 0000h
R/W
04h–07h
PM1_CNT
PM1 Control
PM1a_CNT_BLK 00000000h R/W, WO
08h–0Bh
PM1_TMR
PM1 Timer
PMTMR_BLK
xx000000h
RO
0Ch–0Fh
—
Reserved
—
—
—
10h–13h
PROC_CNT
Processor Control
P_BLK
00000000h R/W, RO, WO
14h–16h
—
Reserved (Desktop Only)
—
—
—
14h
LV2
Level 2 (Mobile/Ultra
Mobile Only)
P_BLK+4
00h
RO
15h
LV3
Level 3 (Mobile/Ultra
Mobile Only)
P_BLK+5
00h
RO
16h
LV4
Level 4 (Mobile/Ultra
Mobile Only)
P_BLK+6
00h
RO
17h–1Fh
—
Reserved
—
—
—
20h
—
Reserved (Desktop Only)
—
—
—
20h
PM2_CNT
PM2 Control (Mobile/
Ultra Mobile Only)
PM2a_CNT_BLK
00h
R/W
28h–2Bh
GPE0_STS
General Purpose Event 0
Status
GPE0_BLK
00000000h
R/WC
2Ch–2Fh
GPE0_EN
General Purpose Event 0
Enables
GPE0_BLK+4 00000000h
R/W
30h–33h
SMI_EN
SMI# Control and Enable
00000000h
R/W, WO,
R/W (special)
34h–37h
SMI_STS
SMI Status
00000000h R/WC, RO
38h–39h ALT_GP_SMI_EN Alternate GPI SMI Enable
0000h
R/W
3Ah–3Bh
ALT_GP_SMI_ST
S
Alternate GPI SMI Status
0000h
R/WC
3Ch–41h
—
Reserved
—
—
—
42h
GPE_CNTL
General Purpose Event
Control
00h
RO, R/W
43h
—
Reserved
—
—
—
44h–45h DEVACT_STS Device Activity Status
0000h
R/WC
46h–4Fh
—
Reserved
Intel ^® ICH7 Family Datasheet
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