307013-003 Datasheet, PDF (603/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

IDE Controller Registers (D31:F1)
15.1.4
Note:
PCISTS — PCI Status Register (IDE—D31:F1)
Address Offset: 06h–07h
Default Value: 0280h
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
15.1.5
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Description
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated by Bus Master IDE interface function.
1 = Bus Master IDE interface function, as a master, generated a master abort.
Reserved as 0 — RO.
Reserved as 0 — RO.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; however, the Intel^® ICH7 does not have a real DEVSEL# signal
associated with the IDE unit, so these bits have no effect.
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Interrupt Status (INTS) — RO. This bit is independent of the state of the Interrupt
Disable bit in the command register.
0 = Interrupt is cleared.
1 = Interrupt/MSI is asserted.
Reserved
RID—Revision Identification Register (IDE—D31:F1)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
Intel ^® ICH7 Family Datasheet
603