307013-003 Datasheet, PDF (611/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

IDE Controller Registers (D31:F1)
15.1.23 SDMA_CNT—Synchronous DMA Control Register
(IDE—D31:F1)
Address Offset: 48h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved
3:2
No Operation (NOP) — R/W. These bits are read/write for legacy software
compatibility, but have no functionality in the Intel^® ICH7.
1
(Desktop
and
Mobile
Only)
Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 1.
1
(Ultra
Mobile
Only)
Reserved
Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.
0
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 0.
15.1.24 SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset: 4Ah–4Bh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Note:
For FAST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to Section 5.16.4
for details.
Bit
15:14
13:12
11:10
9:8
7:6
Description
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the Intel^® ICH7.
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH7.
Reserved
Intel ^® ICH7 Family Datasheet
611