307013-003 Datasheet, PDF (808/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 2 of 2)
Sym
1
Parameter
Mode 3
(ns)
Min Max
Mode 4
(ns)
Min Max
Mode 5
(ns)
Min Max
Measuring
Location
Figure
CRC Word Hold Time at
Sender
CRC word valid hold time at
t92b _{sender (from DMACK#}
6.2
—
6.2
—
10.
0
—
Host
Connector
negation until CRC may
become invalid) (see Note ²)
(Tcvh)
STROBE output released-to-
t93 driving to the first transition 0
of critical timing (Tzfs)
—
0
—
35
—
Device
Connector
23-12
Data Output Released-to-
t94
Driving Until the First
20.
Transition of Critical Timing 0
—
6.7 —
25
—
Sender
Connector
(Tdzfs)
t95
Unlimited Interlock Time
(Tui)
0
—
0
—
0
—
Host
Connector
Maximum time allowed for
t96a
output drivers to release
(from asserted or negated)
—
10
—
10
—
10 See Note 2
(Taz)
t96b
Drivers to assert or negate
(from released) (Tzad)
0
—
0
—
0
—
Device
Connector
Ready-to-final-STROBE time
t97
(no STROBE edges shall be
sent this long after negation
—
60
—
60
—
50
Sender
Connector
of DMARDY#) (Trfs)
t98a
Maximum time before
releasing IORDY (Tiordyz)
—
20
—
20
—
20
Device
Connector
t98b
Minimum time before
driving IORDY (see Note ²)
(Tziordy)
0
—
0
—
0
—
Device
Connector
Time from STROBE edge to
negation of DMARQ or
t99 assertion of STOP (when
sender terminates a burst)
50
—
50
—
50
—
Sender
Connector
23-11
(Tss)
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment – 6 with Packet Interface
(ATA/ATAPI – 6) specification name.
2. See the AT Attachment – 6 with Packet Interface (ATA/ATAPI – 6) specification for further details on
measuring these timing parameters.
808
Intel ^® ICH7 Family Datasheet