307013-003 Datasheet, PDF (628/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.18 INT_PN—Interrupt Pin Register (Audio—D30:F2)
Address Offset: 3Dh
Default Value: See Description
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
This register indicates which PCI interrupt pin is used for the AC '97 module interrupt.
The AC '97 interrupt is internally OR’d to the interrupt controller with the PIRQB#
signal.
Bit
Description
7:0
AC '97 Interrupt Routing — RO. This reflects the value of D30IP.AAIP in chipset
configuration space.
16.1.19 PCID—Programmable Codec Identification Register
(Audio—D30:F2)
Address Offset: 40h
Default Value: 09h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3_HOT to D0 transition. The value in this
register must be modified before any AC ’97 codec accesses.
Bit
Description
7:4 Reserved.
Tertiary Codec ID (TID) — R/W. These bits define the encoded ID that is used to
3:2 address the tertiary codec I/O space. Bit 1 is the first bit sent and Bit 0 is the second bit
sent on ACZ_SDOUT during slot 0.
Secondary Codec ID (SCID) — R/W. These two bits define the encoded ID that is
1:0
used to address the secondary codec I/O space. The two bits are the ID that will be
placed on slot 0, bits 0 and 1, upon an I/O access to the secondary codec. Bit 1 is the
first bit sent and bit 0 is the second bit sent on ACZ_SDOUT during slot 0.
16.1.20 CFG—Configuration Register (Audio—D30:F2)
Address Offset: 41h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3_HOT to D0 transition.
Bit
Description
7:1 Reserved—RO.
I/O Space Enable (IOSE) — R/W.
0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h
0
become read only registers. Additionally, bit 0 of the I/O BARs at offsets 10h and
14h are hardwired to 0 when this bit is 0. This is the default state for the I/O BARs.
BIOS must explicitly set this bit to allow a legacy driver to work.
1 = Enable.
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Intel ^® ICH7 Family Datasheet