307013-003 Datasheet, PDF (641/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Bit
Description
AC-LINK Shut Off (LSO) — R/W.
0 = Normal operation.
3
1 = Controller disables all outputs which will be pulled low by internal pull down
resistors.
NOTE: This bit is not affected by AC ‘97 Audio Function D3_HOT to D0 reset.
AC ’97 Warm Reset — R/W (special).
0 = Normal operation.
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset
will awaken a suspended codec without clearing its internal registers. If software
2
attempts to perform a warm reset while bit_clk is running, the write will be ignored
and the bit will not change. This bit is self-clearing (it remains set until the reset
completes and bit_clk is seen on the AC-link, after which it clears itself).
NOTE: This bit is not affected by AC ‘97 Audio Function D3_HOT to D0 reset.
AC ’97 Cold Reset# — R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry.
All data in the controller and the codec will be lost. Software needs to clear this bit
no sooner than the minimum number of ms have elapsed.
1
1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1.
The value of this bit is retained after suspends; hence, if this bit is set to a 1 prior
to suspending, a cold reset is not generated automatically upon resuming.
NOTE: This bit is in the core well and is not affected by AC ‘97 Audio Function D3_HOT to
D0 reset.
GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of
any GPI causes an interrupt.
0 = Bit 0 of the Global Status register is set, but no interrupt is generated.
0 _{1 = The change in value of a GPI causes an interrupt and sets bit 0 of the Global Status}
register.
NOTE: This bit is not affected by AC ‘97 Audio Function D3_HOT to D0 reset.
NOTE: Reads across DWord boundaries are not supported.
Intel ^® ICH7 Family Datasheet
641