307013-003 Datasheet, PDF (162/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.6.1
5.14.6.2
5.14.6.3
5.14.6.4
5.14.6.5
Conditions for Checking the PCI Clock
When there is a lack of PCI activity the ICH7 has the capability to stop the PCI clocks to
conserve power. “PCI activity” is defined as any activity that would require the PCI
clock to be running.
Any of the following conditions will indicate that it is not okay to stop the PCI clock:
• Cycles on PCI or LPC
• Cycles of any internal device that would need to go on the PCI bus
• SERIRQ activity
Behavioral Description
• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH7
deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.
Conditions for Maintaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the
CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.
• When the ICH7 has tri-stated the CLKRUN# signal after deasserting it, the ICH7
then checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the ICH7 again starts
asserting the signal.
• If an internal device needs the PCI bus, the ICH7 asserts the CLKRUN# signal.
Conditions for Stopping the PCI Clock
• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,
the ICH7 stops the PCI clock by asserting the STP_PCI# signal to the clock
synthesizer.
Conditions for Re-Starting the PCI Clock
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the ICH7 observes the CLKRUN# signal asserted for 1 (free running) clock,
the ICH7 deasserts the STP_PCI# signal to the clock synthesizer within 4 (free
running) clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the
ICH7 again starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the ICH7 re-asserts CLKRUN#,
and simultaneously deasserts the STP_PCI# signal.
LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only)
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA (Mobile
only) or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC devices
running DMA or bus master cycles will not need to assert CLKRUN#, since the ICH7
asserts it on their behalf.
The LDRQ# inputs are ignored by the ICH7 when the PCI clock is stopped to the LPC
devices in order to avoid misinterpreting the request. The ICH7 assumes that only one
more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.
Upon deassertion of STP_PCI#, the ICH7 assumes that the LPC device receives its first
clock rising edge corresponding to the ICH7’s second PCI clock rising edge after the
deassertion.
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Intel ^® ICH7 Family Datasheet