307013-003 Datasheet, PDF (645/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.2.11 SDM—SDATA_IN Map Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
NABMBAR + 80h
00h
No
Attribute:
Size:
Power Well:
R/W, RO
8 bits
Core
Bit
Description
PCM In 2, Microphone In 2 Data In Line (DI2L)— R/W. When the SE bit is set,
these bits indicates which ACZ_SDIN line should be used by the hardware for decoding
the input slots for PCM In 2 and Microphone In 2. When the SE bit is cleared, the value
of these bits are irrelevant, and PCM In 2 and Mic In 2 DMA engines are not available.
7:6
00 = ACZ_SDIN0
01 = ACZ_SDIN1
10 = ACZ_SDIN2
11 = Reserved
PCM In 1, Microphone In 1 Data In Line (DI1L)— R/W. When the SE bit is set,
these bits indicates which ACZ_SDIN line should be used by the hardware for decoding
the input slots for PCM In 1 and Microphone In 1. When the SE bit is cleared, the value
of these bits are irrelevant, and the PCM In 1 and Mic In 1 engines use the OR’d
5:4 ACZ_SDIN lines.
00 = ACZ_SDIN0
01 = ACZ_SDIN1
10 = ACZ_SDIN2
11 = Reserved
Steer Enable (SE) — R/W. When set, the ACZ_SDIN lines are treated separately and
3
not OR’d together before being sent to the DMA engines. When cleared, the ACZ_SDIN
lines are OR’d together, and the “Microphone In 2” and “PCM In 2” DMA engines are not
available.
2 Reserved — RO.
Last Codec Read Data Input (LDI) — RO. When a codec register is read, this
indicates which ACZ_SDIN the read data returned on. Software can use this to
determine how the codecs are mapped. The values are:
1:0 00 = ACZ_SDIN0
01 = ACZ_SDIN1
10 = ACZ_SDIN2
11 = Reserved
NOTE: Reads across DWord boundaries are not supported.
§
Intel ^® ICH7 Family Datasheet
645